Memory modules are provided for increasing the memory capacity of a computer system. Originally single inline memory modules (SIMM) were used in personal computers to increase the memory size. A single inline memory module comprises DRAM chips on its printed circuit board (PCB) only on one side. The contacts for connecting the printed circuit board of the single inline memory module (SIMM) are redundant on both sides of the module. A first variant of SIMMs has thirty pins and provides 8 bits of data (9 bits in parity versions). A second variant of SIMMs which are called PS/2 comprise 72 pins and provide 32 bits of data (36 bits in parity versions).
Due to the different data bus width of the memory module in some processors, sometimes several SIMM modules are installed in pairs to fill a memory bank. For instance, in 80386 or 80486 systems having a data bus width of 32 bits either four 30 pins SIMMs or one 72 pin SIMM are required for one memory bank. For pentium systems having a data bus width of 64 bits two 72 pin SIMMs are required. To install a single inline memory module (SIMM) the module is placed in a socket. The RAM technologies used by single inline memory modules include EDO and FPM.
Dual Inline Memory Modules (DIMM) began to replace single inline memory modules (SIMM) as the predominant type of memory modules when Intels pentium processors became wide spread on the market.
While single inline memory modules (SIMMS) have memory units or DRAM chips mounted only on one side of their printed circuit boards (PCB) a dual inline memory modules (DIMMS) comprise memory units mounted on both sides of the printed circuit boards of the modules.
There are different types of Dual Inline Memory Modules (DIMM). An unbuffered Dual Inline Memory Module does not contain buffers or registers located on the module. These unbuffered Dual Inline Memory Modules are typically used in desktop PC systems and workstations. The number of pins are typically 168 in single data rate (SDR) memory modules, 184 pins in double data rate modules and in DDR-2 modules. DDR-2-DRAMs are a natural extension of the existing DDR-DRAMs. DDR-2 has been introduced at an operation frequency of 200 MHz and is going to be extended to 266 MHz (DDR-2 533), 333 MHz (DDR-2 667) for the main memory and even 400 MHz (DDR-2 800) for special applications. DDR-SDRAM (synchronous DRAMs) increase speed by reading data on both the rising edge and the falling edge of a clock pulse, essentially doubling the data bandwidth without increasing the clock frequency of a clock signal.
A further type of Dual Inline Memory Module (DIMM) is a registered Dual Inline Memory Module. A registered Dual Inline Memory Module comprises several additional circuits on the module in particular a redriver buffer component like a register to redrive command address signals. Further a phase locked loop (PLL) is provided for timing alignments to redrive clock signals. Registered Dual Inline Memory Modules are typically used in highend servers and highend workstations.
ECC- Dual Inline Memory Modules comprise error correction bits or ECC bits. This type of Dual Inline Memory Module has a total of 64 data bits plus 8 ECC bits and is used mostly for server computers. Registered Dual Inline Memory Modules either with ECC or without ECC are used for SDR, DDR and DDR-2.
A further type of Dual Inline Memory Modules are so called small outline DIMM (SO-DIMM). They are an enhanced version of standard Dual Inline Memory Modules and are used in laptops and in some special servers.
A Dual Inline Memory Module comprises a predetermined number N of memory chips (DRAMs) on its printed circuit board. The data width of each memory chip is typically 4 bits, 8 bits or 16 bits. Nowadays personal computer mostly uses a unbuffered Dual Inline Memory Module if a DIMM is selected as the main memory. However, for a computer system with higher main memory volume requirements, in particular a server, registered Dual Inline Memory Modules are the popular choice.
Since memory requirements in a computer system are increasing day by day i.e. both in terms of memory size and memory speed it is desired to place a maximum number of memory chips (DRAMs) on each memory module (DIMM).
FIG. 1 shows a Dual Inline Memory Module according to the state of the art. The Dual Inline Memory Module comprises N DRAM chips mounted on the upper side of the printed circuit board (PCB). The registered Dual Inline Memory Module as shown in FIG. 1 comprises a command and address buffer which buffers command and address signals applied to the Dual Inline Memory Module by a main motherboard and which outputs these signals via a command and address bus (CA) to the DRAM chips mounted on the printed circuit board. A chip selection signal S is also buffered by the command and address buffer and is provided for selecting the desired DRAM chip mounted on the DIMM circuit board. All DRAM chips are clocked by a clock signal CLK which is buffered by a clock signal buffer which is also mounted on the Dual Inline Memory Module (DIMM). Each DRAM chip is connected to the motherboard by a separate databus (DQ) having q data lines. The data bus of each DRAM chip comprises typically 4 to 16 bits.
FIG. 2 shows a cross section of the Dual Inline Memory Module (DIMM) as shown in FIG. 1 along the line A-A′. To increase the memory capacity the DIMM has DRAM chips mounted on both sides of the printed circuit board (PCB). There is a DRAM chip on the top side of the DIMM module and a DRAM chip on the bottom side of the DIMM module. Accordingly the DRAM Dual Inline Memory Module as shown in FIG. 2 comprises two memory ranks or memory levels, i.e. memory rank 0 and memory rank 1.
To increase the memory capacity of a Dual Inline Memory Module (DIMM) further stacked DRAM chips have been developed.
FIG. 3 shows a stacked DRAM chip having an upper memory die and a lower memory die thus providing two memory ranks within one stacked DRAM chip. The two memory dies are packaged within one chip on a substrate. The stacked DRAM chip is connected to the printed circuit board via pads such as solder balls. Dual Inline Memory Modules which have stacked DRAM chips as shown in FIG. 3 on both sides of the printed circuit board have four memory ranks, i.e. two memory ranks on the top side and two memory ranks on the bottom side.
In current computer Dual Inline Memory Modules having two memory ranks are allowed. When increasing the number of memory ranks within the memory systems to four memory ranks or even eight memory ranks the load on the DQ bus and the CA bus as shown in FIG. 1 is increased. For the CA bus the increase of load is not dramatically since the command and address bus (CA) is running at half speed in comparison to the data bus and the command and address buffer redrives the address and command signals applied by the processor on the motherboard to the Dual Inline Memory Module. The increase of memory ranks on the Dual Inline Memory Module however causes an increase of the load of the DQ-data bus which is driven by the controller on the motherboard. The data rate on the DQ-busses is very high in particular when running at DDR-2 data rate. Consequently an increase of the load connected to each DQ data bus deteriorates rates the data signals further so that data errors can not be excluded. Accordingly there is a limitation of the number M of memory ranks within a DRAM chip connected to the DQ-bus of said chip. By limiting the number of memory ranks allowed within a DRAM chip the memory capacity of a Dual Inline Memory is also limited.
The conventional Dual Inline Memory Module as shown in FIG. 1 comprises a DRAM chip selection bus with CS selection lines. Further the Dual Inline Memory according to the state of the art as shown in FIG. 1 selects the memory ranks within each DRAM chip via a memory rank selection bus having S rank selection lines. The number of selection lines of the memory rank selection bus provided on the printed and circuit board of the Dual Inline Memory Module corresponds to the number M of memory ranks provided within each DRAM chip mounted on the printed circuit board. Further the number of signal pins for applying the memory rank selection signal corresponds to the number of memory ranks M within each DRAM chip. When the number M of memory ranks within each DRAM chip is increased the number of signal pins provided at the edge of the printed circuit board of the Dual Inline Memory Module increases proportionally. When for instance each DRAM chip comprises 8 memory ranks the number of signal pins for the memory rank selection is also 8. However the number of signal pins which can be provided at the edge of the dual inline memory module circuit board is limited.